The present invention relates to a semiconductor design technique, and more particularly, to a semiconductor memory device which generates an output enable signal and performs data input and output operation using the output enable signal.
In general, a semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) is inputted with a read command synchronized with an external clock signal and outputs data synchronized with an internal clock signal during read operation. That is to say, not the external clock signal but the internal clock signal is used to output data in the semiconductor memory device. Due to this fact, in the read operation, the read command synchronized with the external clock signal is desired to be synchronized with the internal clock signal. That is to say, in the position of the read command, a clock signal to be synchronized with is changed from the external clock signal to the internal clock signal. This change of a signal to be synchronized with from one clock signal to another clock signal is called “domain crossing.”
In the semiconductor memory device, various circuits for performing domain crossing operation are provided. One of these circuits is an output enable signal generation circuit. The output enable signal generation circuit synchronizes the read command transmitted in synchronization with the external clock signal with the internal clock signal, and outputs an output enable signal. At this time, the output enable signal having completely undergone the domain crossing operation includes CAS latency (CL) information. The semiconductor memory device operates using the output enable signal such that data to be outputted can be outputted at a desired time after the read command as if the data are synchronized with the external clock signal. Meanwhile, CAS latency has information indicating a delay from a timing point that the read command is applied for a unit time corresponding to one period of the external clock signal to a timing point that the data should be outputted. The CAS latency is stored in a mode register set built in the semiconductor memory device. The CAS latency can be used as an index for determining the operating frequency of the semiconductor memory device.
Meanwhile, a skew may occur between the external clock signal and the internal clock signal due to delay factors in the semiconductor memory device. In order to compensate for the a skew, an internal clock signal generation circuit is provided in the semiconductor memory device. Typically, internal clock signal generation circuits include a phase locked loop and a delay locked loop. In the present specification, a DLL clock signal generated by the delay locked loop will be exemplarily used as an internal clock signal.
FIG. 1 is a block diagram illustrating a conventional circuit for generating an output enable signal in a semiconductor memory device.
Referring to FIG. 1, an output enable signal generation circuit includes a counter reset signal generation section 110, an initialization section 120, a DLL clock counting section 130, a delay model section 140, an external clock counting section 150, a latching section 160, and a comparison section 170.
The counter reset signal generation section 110 synchronizes an output enable reset signal RST_OE with a DLL clock signal CLK_DLL and generates a DLL clock counter reset signal RST_DLL. The output enable reset signal RST_OE is a signal that is activated by an external command or an internal signal of a semiconductor memory device when resetting the output enable signal generation circuit.
The initialization section 120 provides an initial counting value corresponding to a CAS latency CL, to the DLL clock counting section 130. That is to say, the initialization section 120 sets an output signal S<0:2> corresponding to the CAS latency CL as the initial counting value of the DLL clock counting section 130.
The DLL clock counting section 130 is reset in response to the DLL clock counter reset signal RST_DLL and counts the DLL clock signal CLK_DLL starting from the initial counting value corresponding to the output signal S<0:2> of the initialization section 120. In other words, the DLL clock counting section 130 generates a DLL clock counting value CNT_DLL<0:2> by counting the DLL clock signal CLK_DLL starting from the initial counting value set according to the CAS latency CL.
The delay model section 140 models a delay difference between an external clock signal CLK_EXT used in a domain crossing circuit and the DLL clock counter reset signal RST_DLL. The delay model section 140 delays the DLL clock counter reset signal RST_DLL by an asynchronous delay time, synchronizes it with the external clock signal CLK_EXT, and generates an external clock counter reset signal RST_EXT.
The external clock counting section 150 is reset in response to the external clock counter reset signal RST_EXT and counts the external clock signal CLK_EXT. In general, the initial counting value of the external clock counting section 150 is set to 0.
The latching section 160 latches an external clock counting value CNT_EXT<0:2> being the output signal of the external clock counting section 150 in response to a read command RD, and outputs a latched external clock counting value CNT_LAT<0:2>.
The comparison section 170 compares the DLL clock counting value CNT_DLL<0:2> and the latched external clock counting value CNT_LAT<0:2> and activates an output enable signal OE at a timing point when the two values become the same. The output enable signal OE outputted in this way is a signal that is synchronized with the DLL clock signal CLK_DLL, and includes the information of the CAS latency CL. Meanwhile, the output enable signal OE is used along with burst length information to output data.
The counter reset signal generation section 110, the initialization section 120, the DLL clock counting section 130, the delay model section 140, the external clock counting section 150, the latching section 160, and the comparison section 170 will be collectively referred to as an “output enable signal generation block.” As a result, the output enable signal generation block is reset in response to the output enable reset signal RST_OE, counts the DLL clock signal CLK_DLL and the external clock signal CLK_EXT, and generates the output enable signal OE corresponding to the read command RD and the CAS latency CL.
Meanwhile, a semiconductor memory device has been developed so as to achieve high integration, high speed operation and low power consumption. In this regard, efforts have been made to minimize power consumed in the operation of circuits. The conventional output enable signal generation block includes the DLL clock counting section 130 for counting the DLL clock signal CLK_DLL and the external clock counting section 150 for counting the external clock signal CLK_EXT. Typically, each of the DLL clock counting section 130 and the external clock counting section 150 can comprise a counter which is composed of a plurality of flip-flops and performs counting operation in response to the corresponding clock signal. The counting operation consumes power.
The DLL clock counting section 130 and the external clock counting section 150 according to the conventional art perform counting operation irrespective of read and write operation after banks of the semiconductor memory device become active until they are precharged. Namely, the semiconductor memory device performs counting operation in read and write operation, whereby power consumption occurs. The present invention described below minimizes power consumption due to a counting operation of semiconductor memory device.